Guarded Signal Assignments

Concurrent Statement---- used in ---->Architecture
label: block (optional_guard_condition) declarations begin concurrent statements end block label;
The label is compulsory CONTROL_LOGIC: block begin U1: CONTROLLER_A port map (CLK,X,Y,Z); U2: CONTROLLER_A port map (CLK,A,B,C); end block CONTROL_LOGIC; DATA_PATH: block begin U3: DATAPATH_A port map (BUS_A,BUS_B,BUS_C,Z); U4: DATAPATH_B port map (BUS_A,BUS_C,BUS_D,C); end block DATA_PATH;
Without a guard condition a block is a grouping together of concurrent statements within an architecture. It may have local signals, constants etc. declared.
Blocks may contain further blocks, implying a form of hierarchy within a single architecture.
A Block may contain any of the declarations possible for an architecture. Items declared within a block are only visible inside it.
IF an optional guard condition is included, the block becomes a guarded block. the guard condition must return a boolean value, and controls guarded signal assignments within the block. If the guard condition evaluates to false, the drive to any guarded signals from the block is "switched off". Such signals must be declared to be guarded signals of a resolved type. Guarded signals can be declared by adding the words bus or register after the name of the type of the signal. The difference between bus and register signals is that if all drivers to a bus signal are "switched off", it requires a resolution function to provide a value for the signal but a register signal retains its last driven value after all drivers to it have been switched off. architecture BLKS of TRISTATE is signal INT: std_logic bus; begin DRIVER_1: block (EN = '1') begin INT <= guarded DATA_1; end block DRIVER_1; end BLKS;
Unguarded block statements are usually ignored by logic synthesis tools (i.i. all blocks within an architecture are "flattened").
Guarded block statements are not usually supported for synthesis.

Sequential (i.e. flip-flop and register) behaviour can be modelled using guarded blocks, but again for synthesis and readability it is better described using "clocked" processes.

In VHDL-93 the keyword block (or the guard condition, if there is one), may be followed by the keyword is, for consistancy.:

label: block (optional guard_condition) is -- etc


Formal Definition

A Boolean-valued expression associated with a block statement that controls assignments to guarded signals within a block. A guard expression defines an implicit signal GUARD that may be used to control the operation of certain statements within the block.

Simplified Syntax

some_signal_in_a_block <= guarded expression;


The characteristic feature of the block statement is the guard expression. It is a logical expression of the Boolean type, declared implicitly after the reserved word block whenever a guarded expression appears inside the block (Example 1).

The guard expression implies a signal named 'guard' at the beginning of the block declaration part. This signal can be read as any other signal inside the block statement but no assignment statement cant update it. This signal is visible only within the given block. Whenever a transaction occurs on any of the signals on the right hand side of the guard expression, the expression is evaluated and the 'guard' signal is immediately updated. The 'guard' signal takes on the TRUE value when the value of the guard expression is true. Otherwise, 'guard' takes on the FALSE value.

The 'guard' signal may also be declared explicitly as a Boolean signal in the block statement. The advantage of this approach is that more complex (than a simple Boolean expression) algorithm to control the guard signal can be used. In particular, a separate process (Example 2) can drive the guard signal.

If there is no guard expression and the guard signal is not declared explicitly, then by default the guard signal is always true.

The guard signal is used to control so called guarded concurrent signal assignment statements contained inside the block. Each such statement contains the reserved word guard placed after the symbol "<=". They assign a new value to the signal only when the guard signal is true. Otherwise, the signal assignment statement does not change the value of the given signal. In Example 1, the signal OUT_1 will take on the value of not IN_1 only when the value of the expression CLS'EVENT and CLK='1' will be true.


Example 1

RISING_EDGE : block (CLK'EVENT and CLK='1')
  OUT_1 <= guardednot IN_1 after 5 ns;
endblock RISING_EDGE;

The assignment to the signal OUT_1 is guarded, which introduces the implicit GUARD signal into the block.

Example 2

ALU : block
signal GUARD: Boolean := False;
  OUT_1 <= guardednot IN_1 after 5 ns;
  P_1: process
      GUARD <= True;
    end process P_1;
endblock ALU;

Signal GUARD is declared explicitly and can be assigned value like any other signal.

Important Notes

  • Guarded blocks are usually not supported for synthesis.


0 thoughts on “Guarded Signal Assignments

Leave a Reply

Your email address will not be published. Required fields are marked *